4014BT Datasheet PDF - NXP

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4014BT
NXP

Part Number 4014BT
Description HEF4014B
Page 13 Pages


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HEF4014B
8-bit static shift register
Rev. 9 — 21 March 2016
Product data sheet
1. General description
The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight
synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a
synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP)
and buffered parallel outputs from the last three stages (Q5 to Q7).
Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH
transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is
HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP.
When PE is LOW, data is shifted to the first position from DS, and all the data in the
register is shifted one position to the right on the LOW-to-HIGH transition of CP. The clock
input’s Schmitt trigger action makes it highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Parallel-to-serial converter
Serial data queueing
General purpose register
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C
Type number Package
Name Description
HEF4014BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1



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5. Functional diagram
 3(
 '6
 &3
Fig 1. Functional diagram
3(
'
HEF4014B
8-bit static shift register
       
' ' ' ' ' ' ' '
' ' ' ' ' ' ' '
&3 6+,)75(*,67(5
%,76
4 4 4
  
DDH
' ' '
'4
'6 ))
&3
&3
Fig 2. Logic diagram
'4
))
&3
'4
))
&3
'4
))
&3
4 4 4
DDH
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 21 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 13



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NXP Semiconductors
HEF4014B
8-bit static shift register
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration SO16
+()%
' 
4 
4 
' 
' 
' 
' 
966 
 9''
 '
 '
 '
 4
 '6
 &3
 3(
DDH
6.2 Pin description
Table 2. Pin description
Symbol
Q5 to Q7
D0 to D7
VSS
PE
CP
DS
VDD
Pin
2, 12, 3
7, 6, 5, 4, 13, 14, 15, 1
8
9
10
11
16
Description
output
parallel data input
ground supply voltage
parallel enable input
clock input (LOW-to-HIGH edge-triggered)
serial data input
supply voltage
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 21 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 13



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NXP Semiconductors
HEF4014B
8-bit static shift register
7. Functional description
Table 3. Function table[1]
Number of clock
Inputs
Outputs
transitions CP DS PE Q5
Serial operation
1 1D L X
2 2D L X
3 3D L X
6 X L 1D
7 X L 2D
8 X L 3D
X X no change
Parallel operation
1 X H D5
X X no change
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW;
= LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition;
8. Limiting values
Q6
X
X
X
X
1D
2D
no change
D6
no change
Q7
X
X
X
X
X
1D
no change
D7
no change
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Tamb = 40 C to +85 C
SO16 package
P power dissipation
per output
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[1]
Min
0.5
-
0.5
-
-
-
65
40
-
-
Max
+18
10
VDD + 0.5
10
10
50
+150
+85
Unit
V
mA
V
mA
mA
mA
C
C
500 mW
100 mW
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 21 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 13



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