4013 Datasheet PDF - Fairchild

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4013
Fairchild

Part Number 4013
Description Dual D-Type Flip-Flop
Page 7 Pages


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October 1987
Revised March 2002
CD4013BC
Dual D-Type Flip-Flop
General Description
The CD4013B dual D-type flip-flop is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent data, set, reset, and clock inputs
and “Q” and “Q” outputs. These devices can be used for
shift register applications, and by connecting “Q” output to
the data input, for counter and toggle applications. The
logic level present at the “D” input is transferred to the Q
output during the positive-going transition of the clock
pulse. Setting or resetting is independent of the clock and
is accomplished by a high level on the set or reset line
respectively.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL: fan out of 2 driving 74L
compatibility: or 1 driving 74LS
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm system
• Industrial electronics
• Remote metering
• Computers
Ordering Code:
Order Number Package Number
Package Description
CD4013BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4013BCSJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4013BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Connection Diagram
Truth Table
Top View
CL D R S Q Q
(Note 1)
 00001
 10010
 x 0 0QQ
x x1001
x x0110
x x1111
No Change
x = Don't Care Case
Note 1: Level Change
© 2002 Fairchild Semiconductor Corporation DS005946
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Schematic Diagrams
Logic Diagram
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Absolute Maximum Ratings(Note 2)
(Note 3)
Recommended Operating
Conditions (Note 3)
DC Supply Voltage (VDD)
0.5 VDC to +18 VDC
Input Voltage (VIN)
0.5 VDC to VDD +0.5 VDC
Storage Temperature Range (TS)
65°C to +150°C
Power Dissipation (PD)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)
260°C
DC Supply Voltage (VDD)
+3 VDC to +15 VDC
Input Voltage (VIN)
0 VDC to VDD VDC
Operating Temperature Range (TA)
55°C to +125°C
Note 2: Absolute Maximum Ratingsare those values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The tables of Recom-
mended Operating Conditionsand Electrical Characteristicsprovide con-
ditions for actual device operation.
Note 3: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 3)
Symbol
Parameter
Conditions
IDD Quiescent Device
VDD = 5V, VIN = VDD or VSS
Current
VDD = 10V, VIN = VDD or VSS
VDD = 15V, VIN = VDD or VSS
VOL LOW Level
|IO| < 1.0 µA
Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VOH HIGH Level
|IO| < 1.0 µA
Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VIL LOW Level
|IO| < 1.0 µA
Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
VDD = 10V, VO = 1.0V or 9.0V
VDD = 15V, VO = 1.5V or 13.5V
VIH HIGH Level
|IO| < 1.0 µA
Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
VDD = 10V, VO = 1.0V or 9.0V
VDD = 15V, VO = 1.5V or 13.5V
IOL LOW Level Output
VDD = 5V, VO = 0.4V
Current (Note 4)
VDD = 10V, VO = 0.5V
VDD = 15V, VO = 1.5V
IOH HIGH Level Output
VDD = 5V, VO = 4.6V
Current (Note 4)
VDD = 10V, VO = 9.5V
VDD = 15V, VO = 13.5V
IIN Input Current
VDD = 15V, VIN = 0V
VDD = 15V, VIN = 15V
Note 4: IOH and IOL are measured one output at a time.
55°C
Min Max
1.0
2.0
4.0
+25°C
Min Typ Max
1.0
2.0
4.0
+125°C
Min Max
30
60
120
0.05
0.05
0.05
0.05 0.05
0.05 0.05
0.05 0.05
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
1.5 1.5 1.5
3.0 3.0 3.0
4.0 4.0 4.0
3.5 3.5
3.5
7.0 7.0
7.0
11.0 11.0
11.0
0.64
0.51 0.88
0.36
1.6
1.3 2.25
0.9
4.2 3.4 8.8 2.4
0.64
0.51 0.88
0.36
1.6
1.3 2.25
0.9
4.2
3.4 8.8
2.4
0.1
105 0.1
1.0
0.1
105
0.1
1.0
Units
µA
V
V
V
V
mA
mA
µA
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AC Electrical Characteristics (Note 5)
TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise noted
Symbol
Parameter
Conditions
CLOCK OPERATION
tPHL, tPLH
Propagation Delay Time
tTHL, tTLH
Transition Time
tWL, tWH
tRCL, tFCL
tSU
Minimum Clock
Pulse Width
Maximum Clock Rise and
Fall Time
Minimum Set-Up Time
fCL Maximum Clock
Frequency
SET AND RESET OPERATION
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
tPHL(R),
tPLH(S)
Propagation Delay Time
tWH(R),
tWH(S)
Minimum Set and
Reset Pulse Width
CIN Average Input Capacitance
Note 5: AC Parameters are guaranteed by DC correlated testing.
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
Switching Time Waveforms
Min
Typ
Max
Units
200 350
80 160
ns
65 120
100 200
50 100
ns
40 80
100 200
40 80
ns
32 65
15
10 µs
5
20 40
15 30
ns
12 25
2.5 5
6.2 12.5
MHz
7.6 15.5
150 300
65 130
45 90
90 180
40 80
25 50
5 7.5
ns
ns
pF
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