25P32 Datasheet PDF - Eon Silicon Solution

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25P32
Eon Silicon Solution

Part Number 25P32
Description EN25P32
Page 30 Pages


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EN25P32
32 Mbit Uniform Sector, Serial Flash Memory
EN25P32
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
32 M-bit Serial Flash
- 32 M-bit/4096 K-byte/16384 pages
- 256 bytes per programmable page
High performance
- 100MHz clock rate
Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
Uniform Sector Architecture:
- Sixty four 64-Kbyte sectors
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Byte program time: 7µs typical
- Page program time: 1.5ms typical
- Sector erase time: 800ms typical
- Chip erase time: 25 Seconds typical
Lockable 512byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 16 pins SOP 300mil body width
- 8 pins SOP 200mil body width
- 8 contact VDFN
- All Pb-free packages are RoHS compliant
Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25P32 is a 32M-bit (4096K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25P32 is designed to allow either single Sector at a time or full chip erase operation. The
EN25P32 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/10/18
Free Datasheet http://www.datasheet4u.com/



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Figure.1 CONNECTION DIAGRAMS
EN25P32
8 - LEAD SOP
8 - CONTACT VDFN
16 - LEAD SOP
This Data Sheet may be revised by subsequent versions
2
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/10/18
Free Datasheet http://www.datasheet4u.com/



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Figure 2. BLOCK DIAGRAM
EN25P32
This Data Sheet may be revised by subsequent versions
3
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/10/18
Free Datasheet http://www.datasheet4u.com/



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SIGNAL DESCRIPTION
EN25P32
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted
out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle is
in progress. When CS# is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After power-up, CS# must
transition from high to low before a new instruction will be accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,
while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register Protect
(SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol
CLK
DI
DO
CS#
WP#
HOLD#
Vcc
Vss
Pin Name
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Enable
Write Protect
Hold Input
Supply Voltage (2.7-3.6V)
Ground
This Data Sheet may be revised by subsequent versions
4
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/10/18
Free Datasheet http://www.datasheet4u.com/



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